1. Field of the Invention
The present invention relates to techniques for accurately determining power consumption within an integrated circuit (IC) chip. More specifically, the present invention relates to a method and apparatus for determining power consumption in an IC chip by using one or more test structures located on the IC chip.
2. Related Art
Because of manufacturing variations, ICs exhibit differences in their device-level power-consumption characteristics which are caused by differences in parasitic capacitances and resistances, and differences in the performance between the n-channel and p-channel field effect transistors (n-FETs and p-FETs).
More specifically, dynamic power dissipation and static power dissipation can vary between ICs that are identically designed because of differences introduced during fabrication. These variations affect both static and dynamic power dissipation. Note that dynamic power dissipation is often a significant portion of the overall power dissipation. The manufacturing variations that affect dynamic power dissipation are subtle and include:
1. vertical distance between the wiring layers;
2. dielectric constant for the field oxide;
3. dielectric constant for the gate oxide;
4. gate-oxide thickness;
5. threshold voltages for the n-FETs and p-FETs;
6. carrier mobility for the n-FETs and p-FETs;
7. channel length for the n-FETs and p-FETs; and
8. cross-sectional wire area.
There are two major components of dynamic power consumption: capacitive charging/discharging power and short-circuit power. Many of the above-mentioned variations result in a change in the driven capacitance for a circuit node, which affects capacitive charging/discharging power. Note that the power required to charge and discharge a capacitance, C, is given by:Pcap=FCV2 where F is the frequency and V is the voltage potential across the capacitor. As can be inferred from this equation, changes in capacitance will cause corresponding changes in capacitive charging/discharging power.
Short-circuit power dissipation is caused by current that flows directly from the power-supply rail to the ground rail during the switching of a circuit node between logical states (for example, a transition from a high state to a low state), is given by:
      P    sc    =      F    ⁢                  ⁢          β      12        ⁢                  (                              V            dd                    -                      V            th                          )            3        ⁢          t      rf      (See Neil H. E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design—A Systems Perspective, Second Edition, Addison-Wesley Publishing Company, 1993.)
FIG. 1 presents a voltage-versus-time graph illustrating several factors affecting short-circuit power consumption. First, variations in the threshold voltage for the p-FETs and n-FETs (Vthp and Vthn) increases or decreases the time interval when both the n-FETs and the p-FETs conduct. Likewise, longer rising or falling edge times (trf) also extends the amount of time that both the n-FET and the p-FET conduct.
For a fixed supply voltage, an IC that can be clocked at a higher frequency typically has a smaller threshold voltage than an IC that must be clocked at a lower frequency. A small threshold voltage increases the interval in FIG. 1 when both n-FET and p-FET devices are conducting. Slow devices have longer rise and fall times which also increase the duration of interval when both types of devices conduct.
Mismatched stages of logic, in which an undersized stage drives an oversized stage, can cause the “both on” region to increase for the oversized stage. This is because the slow-rising or slow-falling edge output from the undersized stage causes excess power dissipation in the oversized stage. For example, FIGS. 2A, 2B, and 2C illustrate circuit topologies that cause slow-rising and slow-falling edges, which thereby contribute to larger short-circuit power dissipation. More specifically, FIG. 2A illustrates a small driver driving a large driver, FIG. 2B illustrates a driver driving extra capacitance, and FIG. 2C illustrates a driver driving extra resistance between logic stages.
Static-power dissipation can be determined by applying power to an IC with all of its clock-circuit outputs turned off. The resulting power dissipation (derived from the quiescent IDDQ current) is a measure of the static power dissipation of the IC and can be further parametrically refined by taking measurements at different temperatures and at different supply voltages. Unfortunately, dynamic power consumption cannot be parametrically measured during normal operation of an IC using existing techniques.
Hence, what is needed is a method and an apparatus for determining the power consumption variations of an IC chip without the problems described above.